[j-nsp] MPC7 / QSFP28 I2C issue

[Theo Voss]

Hi all,

we’re experiencing a strange issue on MPC7, configured for 2x40G 4x100G. On two different routers, two different QSFP28 (not same PIC/Port) ports on MPC7 do not recognize the inserted 100G LR4 transceiver while showing I2C errors. We’ve already exchanged the transceiver and verified that the transceivers are OK. Next step is a PIC and FPC reboot, then JTAC case. Just wanted to check if someone has seen an identical issue?

Model: mx480
Junos: 17.3R3-S1.5

FPC 0 REV 43 750-056519 MPC7E 3D MRATE-12xQSFPP-XGE-XLGE-CGE
PIC 0 BUILTIN BUILTIN MRATE-6xQSFPP-XGE-XLGE-CGE
Xcvr 0 850nm 740-032986 QSFP+-40G-SR4
Xcvr 2 850nm 740-058734 QSFP-100GBASE-SR4
Xcvr 5 850nm 740-058734 QSFP-100GBASE-LR4
PIC 1 BUILTIN BUILTIN MRATE-6xQSFPP-XGE-XLGE-CGE
Xcvr 0 850nm 740-032986 QSFP+-40G-SR4
Xcvr 2 NON-JNPR QSFP-100GE-DWDM2
Xcvr 5 NON-JNPR UNKNOWN *** AFFECTED ***

Transceiver 0/5 is 3rd party (Flexoptix), we also tried different modules from different production badges.
The DWDM2 is a PAM4 transceiver, which works well on other fully-utilized MPC7 cards.

Dec 6 20:16:40 fpc0 qsfp_tk_eeprom_scanning_check: qsfp-0/1/5 failed scanning eeprom addr 0x0 err 4294967285
Dec 6 20:16:41 fpc0 qsfp_tk_read_los: qsfp-0/1/5: failed to read at reg offset 0x3
Dec 6 20:17:08 fpc0 qsfp_tk_read_los: qsfp-0/1/5: failed to read at reg offset 0x3
Dec 6 20:17:09 fpc0 qsfp-0/1/5: I2C access failures exceeded 10 times, disable periodic. Please re-insert or replace the optics

Thanks,
Theo
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[Jared Mauch]

Post by Theo Voss
Hi all,
we’re experiencing a strange issue on MPC7, configured for 2x40G 4x100G. On two different routers, two different QSFP28 (not same PIC/Port) ports on MPC7 do not recognize the inserted 100G LR4 transceiver while showing I2C errors. We’ve already exchanged the transceiver and verified that the transceivers are OK. Next step is a PIC and FPC reboot, then JTAC case. Just wanted to check if someone has seen an identical issue?

I don’t know the electrical design of the MPC7 but ideally you want either to be doing a bitbang i2c or be going via an i2c mux. I’ve seen issues with cheaper optics and not handling the higher i2c rates, eg: over 100. You start to see errors when asking them to respond.

I ask my vendors to make sure they’re implementing reading of all the SFF reading relevant for the optic families that we use. Make sure you ask and specify a revision number, eg: version 12.2 of the document, or sff-8690 if your hardware needs that.

- Jared

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[Aaron Gould]

Not sure if it helps, but here's what I'm running successfully in mine


{master}
***@blvr-960> show version | grep "Junos:|model"
Model: mx960
Junos: 17.4R1-S2.2


{master}
***@blvr-960>

{master}
***@blvr-960> show chassis hardware | grep "mrate|100G"
FPC 0 REV 43 750-056519 (removed) MPC7E 3D MRATE-12xQSFPP-XGE-XLGE-CGE
PIC 0 BUILTIN BUILTIN MRATE-6xQSFPP-XGE-XLGE-CGE
Xcvr 2 REV 01 740-058734 (removed) QSFP-100GBASE-SR4
Xcvr 5 NON-JNPR (removed) QSFP-100GBASE-LR4
PIC 1 BUILTIN BUILTIN MRATE-6xQSFPP-XGE-XLGE-CGE
FPC 11 REV 43 750-056519 (removed) MPC7E 3D MRATE-12xQSFPP-XGE-XLGE-CGE
PIC 0 BUILTIN BUILTIN MRATE-6xQSFPP-XGE-XLGE-CGE
Xcvr 2 REV 01 740-058734 (removed) QSFP-100GBASE-SR4
PIC 1 BUILTIN BUILTIN MRATE-6xQSFPP-XGE-XLGE-CGE


-Aaron


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